1. Field of the Invention
This invention relates generally to input buffer circuitry, and, more particularly, to an input buffer implemented with a high-speed, differential pair.
2. Description of Related Art
Buffer circuitry is commonly used to interface electrical circuits. There are at least three significant considerations in the design of a buffer circuit: speed, timing, and power. The speed consideration of a buffer circuit refers to how fast the buffer circuit transitions from one logical state to another (e.g., high-to-low or low-to-high). A buffer circuit that has a transition time slower than the circuits that it interfaces will slow the overall operation of the device. That is, while the interfaced circuits may be designed for optimum operation at a preselected speed, a slow interface circuit may prevent the interfaced circuits from achieving their desired optimal speed.
The timing consideration of the buffer circuit is closely related to the speed consideration, but refers to variations in the transition time of the buffer circuit. That is, many interfaced circuits have critical timing requirements that will not tolerate variations in transition times. Prior art buffer circuits are known to be sensitive to variations in their loads. Different loads will result in different transition times for the same buffer circuit. Thus, designers have typically designed buffer circuits with load as a design parameter. In other words, designers have been forced to design a different buffer circuit for every different loads. In a typical electrical component, such as a microprocessor, thousands of different buffer circuits may be needed, requiring numerous buffer designs. This duplicative design effort is plainly inefficient and expensive.
The power consideration of the buffer circuit refers to the amount of power consumed to operate the buffer circuit. High power consumption is a significant disadvantage in all electrical circuits where heat dissipation is a consideration, as power consumed is directly related to heat produced. Additionally, high power consumption is particularly problematic in battery operated devices, such as portable computers, as increased power consumption directly leads to reduced battery life.
These three design considerations are often at odds with one another. For example, designers have attempted to improve the timing characteristics of buffer circuits by employing a differential pair. The use of a differential pair improves timing by insuring that the transition from one state to another occurs at a precisely controlled voltage level. However, there is a direct tradeoff between the speed of a conventional differential pair verses the amount of biasing current flowing through the differential pair. Thus, increasing the speed of the conventional differential pair will increase the biasing current or power consumed by the conventional differential pair.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.